The ET-SoC-1, interactivelyET-SoC-1

27 September 2026, second version the same day, the broadcast flow 28 September, the routes as measured 29 September (replies y first, on three cards), the zoom 30 September, down to the quarks 1 October · every number is a fact with a source: a repository file and field, a manual page, or a source line · the chip's facts: the table below, built in the repository's docs/reports/data/2026-09-27-chip-diagram · part of the ET-SoC-1 measurement reports

A schematic of Esperanto's ET-SoC-1 that you can click through: the die with its mesh of shires, a shire with its cache and minions, a minion with its vector unit, whose lanes also run the tensor instructions. Eleven animated flows show where data goes and what it costs, with the latency, bandwidth, energy and heat measured on the lab's cards, the host link included. A tour steps through it all.

How to use it

• Click any part (or Tab to it and press Space) for what it is, its numbers with their units and card coverage, a link to the report that measured them, and, where the drawing infers something, what would settle it. Point at a number to see its source; from the keyboard, Tab to a fact in the details list.
• Zoom in with a double-click on a part (a double-tap on a touch screen, or the Zoom in button that a tap shows under the drawing), Enter on a focused part, the + key, or the zoom buttons under the part's text in the details panel. A click only selects. A part with no closer drawing says so in the panel and offers the zooms it has.
• Zoom out with the wide ↑ Zoom out button above the drawing, Backspace or the − key: out past the package, the card and its host to the rack the lab's machines stand in. Beside it, the breadcrumb jumps to any level (the outer ones fold into its "…" menu), and the readout gives the size of what you see, in metres and as a power of ten. A second press while the camera moves goes one further. Past the rack the button only says "?". Keep pressing and the zoom goes round a loop, always outward: past the largest scale it comes back at the smallest, the Planck length, and climbs from there through a quark, a proton and an atom to the chip again (+ goes round the other way).
• Switch (G): the transistor-level drawings have two states, drawn both ways: the gate at 0 V or at the minion rail's 0.517 V (the FinFET, its fin and its channel fill with electrons), an inverter's input 0 or 1, a stored bit 0 or 1, a DRAM cell just written or 32 ms later. Press the switch in the drawing, the panel's button or G.
• Sideways. Inside a shire, the names at its four edges ("→ shire 28", "↓ shire 29") are links: click one (or Tab to it and press Enter) to glide sideways to that shire, memory shire, PCIe or I/O shire. With no flow or tour on the stage, the arrow keys do the same, and in a minion, a memory shire or any scale with neighbours glide to the one that way.
• Flows 1 to 9, 0 and B animate a load that misses to DRAM, the latency ladder, TensorSend across the mesh, the relay against DRAM, gathers and scatters, the host over PCIe (timed on three cards), a matmul on the tensor unit, the same matmul's watts and heat on different data, one hot line stopping a shire, the allreduce tree, and one value broadcast to every minion four ways (B, which the tour leaves out). Each flow is a row of stages under the drawing: click one, or step with the Left and Right arrows. Space pauses everything that moves, the camera included; stepping while paused shows each stage's end state. The 1× button beside Play (or S) plays the flows and the tour at double speed, 2×, and back: the stages, the packets, the charts and the camera's moves all go twice as fast, and your own zooms keep their pace.
• Follow (C): the camera follows the flow from scale to scale. Turn it off, or zoom yourself, and the camera stays: a stage on the die then plays in a small picture of the die in the corner, and a stage inside a shire or a minion marks its place. Stepping turns following back on after your own zoom.
• Tour (T) steps through seventeen slides: the arrows (or a clicker's PageDown and PageUp) step the stages of each flow and move on at its ends; Shift with an arrow, a click on a dot or on a slide's name in the bar, or a flow's key jumps to a slide; Q or End tour ends the tour, and T picks it up where it was left. Esc never ends it.
• Presenting (the tour, or F): the panel's text is larger, its fact lists, asks and buttons are hidden, numbers lose their dotted underline and the pointer hides when it rests. F (or Present) goes full screen. Where the page's frame forbids that, the stage fills the frame instead and offers the browser's own full screen (F11) and a presenter window, a copy of this page in a window of its own where F works. P hides the details panel, D switches light and dark. The same from the address: ?theme=light, ?panel=off, ?flow=7, ?tour=1, and any level with ?at= (?at=rack, ?at=shire:20/minion:20.1.3). The stage fits one screen from 1280 × 720 up. On a phone the drawing fits the screen's width: the die with its packages at the chip's scale, a shire or a minion at theirs, and a flow's charts under the die. The levels outside the chip show their middle, with larger type. A minion's labels, and those of the circuits inside it, are small there: pinch to enlarge them, or tap a part for its details.
• Links. The address follows what the stage shows, so that a link opens the same thing: a flow as #flow=8-data-watts (the key alone works too, #flow=8), with &stage=3 while you hold it at a stage (paused, or stepped while paused); a still slide of the tour as #tour=3; a flow or the tour played at 2× adds &speed=2 (#flow=8-data-watts&speed=2) and opens at 2×; and with nothing playing, the scale the camera rests on, as ?at= names it (#at=rack, #at=shire%3A20/minion%3A20.1.3). On spacesheep it shows in your own address bar. Copy link, under the details panel (on a phone, under the caption), copies the link to what is shown; where the page's frame forbids the clipboard it shows the link selected, to copy with Ctrl-C. Such a link wins over ?flow=, ?tour= and ?at=, and changing it in the address bar takes the stage there.

From the rack to the quarks

Since 30 September the zoom goes on past the chip in both directions, at the owner's request. Out from the die: the package under its lid, the PCIe card (the vendor's photo), a host computer (an ATX board drawn to scale) and the rack of open-frame machines the lab's hosts stand in (the owner's photo, its machines' labels blurred). Most levels say what light, or a signal in a fibre, takes to cross them, counted in ticks of the cards' usual 600 MHz clock.

In from the die, every part opens. The memory system goes down as the anatomy of a memory access draws it (its drawings are reused here): the L1 data cache to an LRAM block, a row and one latch's transistors; the shire cache to a bank, a sub-bank, an SRAM panel and a 6T cell; a mesh hop to its wire and repeaters; a memory shire to its PHY and a DQ driver; the DRAM to a bank and its 1T1C cell, and that cell in section (on a DRAM process, not the chip's). Since 1 October every transistor-level drawing leads on into the device: the latch's inverters, the 6T cell's transistors, the repeaters, the level shifters and the DQ pin's driver. The blocks whose insides are described but not drawn by Esperanto (the mesh stop and its router, the crossbar, the UC block, a neighbourhood, the core, the vector unit and its lanes, the tensor sequencer, the PCIe and I/O shires) are logical drawings built from what the documents say. And the compute path goes all the way down: a vector lane's fused multiply-add, its compressor tree of 17 partial products, one column of it, a 4:2 compressor, a full adder, an XOR gate in transistors, then the device.

Every part leads further in. Where the chip's own circuit is not published (all of its gate-level design), a block opens onto the construction the textbooks give, labelled "textbook construction": the multiply-add's adder is a Kogge-Stone prefix tree, its aligner and normaliser shifters of multiplexers, its partial products a radix-4 Booth encoder's, its leading-zero count a tree of small cells; register files, decoders, queues, counters, comparators, control logic of standard cells, a phase-locked loop, error correction, a ROM, a sense amplifier and a clock gate are drawn the same way. Each goes down to a gate drawn as transistors (NAND, NOR, AND-OR-INVERT, XOR, an inverter, a multiplexer), and every gate to the FinFET, its fin, its channel and the silicon atoms; the DRAM's parts go to the DRAM cell's own transistor instead. A PCIe lane opens as a serial link, block by block (serialiser, equaliser and driver; the receiver's equaliser, samplers and clock recovery), down to a differential amplifier and a sense amplifier; the crossbars are multiplexers and arbiters; the multiply-add's rounding is a sticky bit, a decision and an increment. The wiring opens onto copper wires in section and a copper atom, whose outer electron is the current. Off the chip, the card's regulators open a buck converter, whose switches are power transistors of their own (not N7 FinFETs), and its boot switches the pin they set and the chip's receiver; the host's processor, memory and supply open the constructions they share with the chip's, each saying it is not the ET-SoC-1's. Only the die's key, a legend, has no zoom. Sideways, the memory shires, the PCIe shire and the I/O shire have the shires' edge links, so every move to a neighbour has its way back.

The device is drawn at TSMC N7's published numbers (the chip is made in TSMC's 7 nm, N7 by WikiChip's account): the FinFET with its gates 57 nm apart and its fins 30 nm apart in a cell 240 nm tall; a fin in section, 6 nm wide and 52 nm tall, under a gate stack of hafnium oxide and work-function metal (the industry's practice: TSMC does not publish N7's); the channel under the gate, 16.5 nm long, about 257,000 silicon atoms and almost no dopant atoms; and one cell of the silicon crystal with its band gap. Below that the ladder goes on: one silicon atom with its fourteen electrons, its nucleus of 14 protons and 14 neutrons, a proton's three quarks, a quark with no measured size, and the Planck length, where known physics stops. Beside them: an electron, a phosphorus dopant atom, the DRAM cell, a copper atom of the wiring and a power transistor of the card's regulators.

The electronics. The scenes of the device say how it works, with this chip's own numbers where the repository has them: the gate at 0 V or at the minion rail's 0.517 V (the switch, or G), about 85-120 electrons in an "on" channel and 0.002 on average in an "off" one, which still lets some 10 billion a second leak through (an average: the chip's leakage at 80 °C shared over its transistors); roughly a thousand electrons on an SRAM bit's node, 45,000-70,000 in a DRAM cell, which leaks and must be refreshed every 32 ms; the band gap that keeps pure silicon an insulator; and the energy of a switch, which goes as the voltage squared, the whole of the chip's low-voltage design. Numbers that are estimates say so and carry their assumptions.

How many electrons?

What it takes, in electrons, for the chip to do one small thing: each number with its kind and source (point at it); an estimate says "about" and its assumptions are in its source.

The camera moves between levels in three ways. Where one level is drawn inside the other it zooms smoothly. Where the ratio is huge, or the two pictures are of different kinds, it makes a "powers of ten" jump: it zooms into a marked box while the next level grows out of it, and the readout sweeps the decades in between (from a silicon atom to its nucleus, from a proton to a quark). Between neighbouring shires it glides sideways. Each level's facts, with their kinds and sources, are in its details panel and in the table below.

Honesty notes. Sizes from the shire down are estimates (marked ≈): no floorplan of the chip's inside is published, so the blocks are logical drawings, and the circuits are textbook circuits (each says so) tied to this chip by its documents' counts and names. Facts read from core-et's Erbium-branch RTL carry that caveat: the same Minion core lineage in a later configuration, not confirmed to match the silicon. TSMC's N7 pitches, fin and gate length are published; this chip's own cells, its layer count and its transistors' threshold voltages are not. The pictures of the atom, the nucleus and the proton say what they are: electrons are clouds, not orbits, and quarks are not little balls. The rack photo is the page author's own, with the machines' tape labels blurred (they carry host names and network addresses); which three machines are the lab's is not recorded, so the host shown is "one of the rack's machines". The card photo is the vendor's (Apache-2.0), not a lab card.

What the diagram shows

What is measured, what is specified, what is inferred

What would settle the rest: the asks

Every part the drawing infers, what would settle it, and the row on the hub's improvement ladder that asks for it (a document to request from AI Foundry, an experiment on the cards, or an interface). The hub collects them with everything else the instruments cannot see.

Every fact on this page

The facts behind the diagram, the panels and the captions, with their kind, the cards they were measured on and their source. Sort by any column or filter the rows.

Versions

• 27 September 2026: the die, a shire and a minion, ten flows and the tour; a second version the same day.
• 28 September: the broadcast flow (B).
• 29 September: the routes as measured on three cards (a reply goes y first, back along its request's links), where a host copy lands, the DRAM address map.
• 30 September: the zoom out past the chip (the powers-of-ten ladder above the die) and in to the circuits (the caches' cells and the DRAM's, a vector lane's adder down to a FinFET and the silicon crystal), double-click to zoom into any part, the wide ↑ Zoom out button and the breadcrumb above the drawing, the panel's zoom buttons, the shires' edge arrows as links that glide to the neighbouring shire, and a smoother camera (one ease per move, blended through each scale).
• 1 October: the ladder shared with the memory levels' page; the device at TSMC N7's published numbers (the fin 6 by 52 nm, the gate 16.5 nm, the channel 257,000 atoms); on down to a silicon atom, its nucleus, a proton, a quark and the Planck length, with an electron, a dopant atom and a DRAM cell beside them; the electronics drawn in two states (the switch, or G); every transistor-level drawing leads on into the device; and Esperanto's and N7's facts placed scale by scale. Later the same day: every part leads further in, through textbook constructions where the chip's own circuit is not published, down to a transistor and its atoms; and the memory, PCIe and I/O shires got the shires' edge links, each with its way back. Last, a walk of every scene by its path closed the remaining gaps: a PCIe lane, the crossbars, the rounding, the copper wiring and its atom, the card's regulators and boot switches, and the host's parts now lead down to a transistor drawn as such and its atoms.
• 1 October, links: each flow and each scale has an address you can copy (Copy link): the address follows the flow, its held stage, the tour's slide or the scale shown, and opening it goes there.
• 1 October, speed: the replay plays at 1× or 2× (the button beside Play, or S), and a link to a flow or the tour played at 2× opens at 2× (&speed=2).
• 1 October, evening: Up past the top goes straight to the Planck length; the loop runs one way.
• 1 October, late: four reviews' fixes: the landing after the loop says it is no journey through space and names the atom it lands under; facts corrected (an Alexander phase detector's early and late, an atom's inner electrons' binding, the nucleus's size against the atom's, the source's active dopants, PCIe's eleven presets, a few attributions); the sense amplifier, the multiplexer, the adder's carries, the ROM and the decoder drawn right; the stored bit's box clear of the 6T cell; labels fade during moves; the side links of the memory, PCIe and I/O shires drawn as pills.

Related reports

• Over the PCIe link — the host link timed on three cards on 27 September: copy bandwidth from 4 KB to 256 MB, staged and DMA-only, small copies and the runtime's polling, kernel launches.
• On-chip communication — the measured map of the 32 compute shires and what messages cost inside a neighbourhood, a shire and across the mesh.
• Anatomy of a memory access — one load traced from L1 to DRAM; the memory-shire fit the diagram places the memory shires by.
• Memory hierarchy — latency, bandwidth and energy at every level.
• The Horace experiment — the same matmul on different data: the watts, the heat and the tensor unit's timings.
• One hot line stops a shire — a contended atomic is fair, and stops its home shire's own traffic at 22 requesters.
• Heat per millimetre — the die's dimensions, the tile pitch and what a bit costs per millimetre of mesh.
• Hand it to the next shire — the relay against a round trip through DRAM.
• The energy manual — what each instruction, level and message costs.
• Matmul efficiency — the tensor matmul on all 1,024 minions against its peak.
• Limits of observability — the hub: every report, what the instruments cannot see, and the asks.

← All ET-SoC-1 measurement reports